Analysis of Low-Power and Area-Efficient Shift Registers using Pulsed Latch

Flip-flops is perilous timing elements in digital circuits which have a huge influence on the circuit speed and power consumption. The performance of flip-flop is an significant element to regulate the efficiency of the entire synchronous circuit.This paper recommends a low-power and area-efficient shift register using pulsed latches. Therefore area and power consumption are reduced by substituting flip-flops with pulsed latches. This technique explains the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals as an alternative of the conventional single pulsed clock signal. Also the shift register uses a small number of the pulsed clock signals by grouping the latches to more than a few sub shifter registers and using supplementary temporary